The disclosed subject matter relates generally to manufacturing and, more particularly, to a method and apparatus for randomizing dispatch order for single wafer processing.
A semiconductor fabrication facility typically includes numerous processing tools used to fabricate semiconductor devices. The processing tools may include photolithography steppers, etch tools, deposition tools, polishing tools, rapid thermal processing tools, ion implantation tools, and the like. Conventionally, wafers are grouped into lots (e.g., 25 wafers) housed in a common carrier. Wafer lots are processed in the tools, and each processing tool modifies the wafers according to a particular operating recipe so that a desired product is formed in or on the wafer. For example, a photolithography stepper may be used to form a patterned layer of photoresist above the wafer. Features in the patterned layer of photoresist correspond to a plurality of features, e.g. gate electrode structures, which will ultimately be formed above the surface of the wafer. When processing of the wafer is complete, the various features formed in or on the wafer, as well as features formed in or on layers that are deposited above the wafer, combined to form the desired product. Exemplary products include processors, memory elements, and the like.
During the flow of wafers through the fabrication facility, dispatch rules are typically employed to determine the processing order of the lots. Typical dispatch rules attempt to address queue times and priorities of the lots. For example, the lots waiting in the queue the longest are typically dispatched first. This dispatch technique is generally referred to as a first-in/first-out (FIFO) dispatch rule. However, in some cases the lots in the queue may have different priorities. In such cases a lot that has a higher priority (e.g., high value product lot, engineering lot, pilot lot, etc.) may be dispatched prior to a lot that has been in the queue longer, but has a lower priority.
Within a particular lot, wafers are typically identified, sorted, and randomized using a tool referred to as a wafer sorter. The wafer sorter shuffles the wafers periodically to reduce the likelihood that position oriented defects will be introduced in the wafers. If the wafers in the lot were to be processed in the same positions throughout the production flow, defects would typically compound, thereby reducing the yield of the devices.
As the diameter of the wafers has increased, tool manufacturers have moved away from batch processing (e.g., multiple wafers processed concurrently) toward single wafer processing. In a single wafer processing environment, lot based organizational techniques and dispatch rules are less useful. Moreover, wafer sorters are limited resources that have the potential to cause bottlenecks.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the disclosed subject matter described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the disclosed subject matter. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The disclosed subject matter is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.